Voltage Comparison Based High Speed & Low Power Domino Circuit for wide fan-in Gates

This paper presents design of wide fan-in gate for low power and high speed operations with reduced transistor count. In this work some circuital modifications are done to reduce the number of stacked transistor between input and output hence reducing the delay of the designed wide fan-in OR-gate. Also the average power dissipation of the circuit is reduced as it has less number of switching nodes. The idea used in this technique is the use of basic sense amplifier for comparing voltage generated at the two terminals of the logic block of designed circuit. This logic block represents 8, 16, 32 and 64-input OR-gate. The simulations are done for wide fan-in OR-gates using 90nm CMOS technology model with supply voltage of 1V at 110 degrees C of temperature at clock frequency of 1GHz. The simulation results obtained is compared for 32-input OR-gate with standard voltage comparison based domino circuit for delay, average power and PDP which gives 2.5%, 6% and 9% improvements over it respectively.