Identifying Representative Regions of Parallel HPC Applications: a Cross-architectural Evaluation

As high performance computing (HPC) systems reach exascale proportions, the cost of simulation in time and resources increases. Tools for selecting representative parts of parallel applications to reduce simulation cost are widespread, e.g., BarrierPoint achieves this by analysing abstract characteristics such as basic blocks and reuse distances. However, architectures new to HPC will have a limited set of tools available. In this work, we provide a cross-architectural evaluation, on Intel and ARM, of a methodology used to identify representative regions of interest of parallel HPC proxy applications, selected based on abstract characteristics. We observe that we can predict the performance of full application execution by running shorter representative sections. This enables a total simulation time reduction of between 2.5x to 166x, whilst keeping the error below 3.3% for cycles and instructions.