Implementation of Memory Stacking on Logic Controller by Using 3DIC 300mm Backside TSV Process Integration

被引：0

作者：

Chen, Shang-Chun ^{[1
]}

Tzeng, Pei-Jer ^{[1
]}

Hsin, Yu-Chen ^{[1
]}

Wang, Chung-Chih ^{[1
]}

Chang, Po-Chih ^{[1
]}

Chen, Jui-Chin ^{[1
]}

Chang, Yiu-Hsiang ^{[1
]}

Chen, Tsuen-Sung ^{[1
]}

Hsu, Tzu-Chien ^{[1
]}

Chang, Hsiang-Hung ^{[1
]}

Zhan, Chau-Jie ^{[1
]}

Lee, Chia-Hsin ^{[2
]}

Chou, Yung-Fa ^{[2
]}

Kwai, Ding-Ming ^{[2
]}

Ku, Tzu-Kun ^{[1
]}

Wang, Pei-Hua ^{[1
]}

Lo, Wei-Chung ^{[1
]}

机构：

[1] Ind Technol Res Inst, Elect & Optoelect Res Labs, Rm 200,Bldg 17,195,Sec 4,Chung Hsing Rd, Hsinchu 310, Taiwan

[2] Ind Technol Res Inst, Informat & Commun Res Labs, Rm 200,Bldg 17,195,Sec 4,Chung Hsing Rd, Hsinchu 310, Taiwan

来源：

2016 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Technologies of backside via-last TSV (BTSV) 3DIC 300mm process integration are developed to be applied in industry cooperation and mass production business model view. In this work, a successful BTSV process integration is disclosed and applied on 65nm logic controller/45nm DRAM stacking structure. Key enabling process technologies in BTSV formation and thin wafer handling are discussed. The electrical measurement data and functional logic circuit test show the practicability of BTSV integration.

引用

页数：2

共 10 条

[1] Technologies and Challenges of Fine Pitch Backside Via-last TSV Process Integration for 3DIC Applications
Ku, T. K.
Lin, C. H.
Tzeng, P. J.
Chen, E. H.
Hsu, T. C.
Chen, S. C.
Wang, C. C.
Chen, J. C.
Chen, C. C.
Hsin, Y. C.
Liao, S. C.
Chang, P. C.
Lin, Y. M.
Chang, Y. H.
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2013 (CSTIC 2013), 2013, 52 (01): : 3 - 6
[2] Technologies and Challenges of Fine-pitch Backside Via-last 3DIC TSV Process Integration and Its Electrical Characteristics and System Applications
Chen, Erh-Hao
Hsu, Tzu-Chien
Lin, Cha-Hsin
Tzeng, Pei-Jer
Wang, Chung-Chih
Chen, Shang-Chun
Chen, Jui-Chin
Chen, Chien-Chou
Hsin, Yu-Chen
Chang, Po-Chih
Chang, Yiu-Hsiang
Chen, Shin-Chiang
Lin, Yu-Ming
Liao, Sue-Chen
Ko, Cheng-Ta
Zhan, Chau-Jie
Chang, Hsiang-Hung
Chien, Chun-Hsien
Chou, Yung-Fa
Kwai, Ding-Ming
Lo, Wei-Chung
Ku, Tzu-Kun
Kao, Ming-Jer
PROCEEDINGS OF TECHNICAL PROGRAM - 2014 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATION (VLSI-TSA), 2014,
[3] Integration and Optimization of 300 mm Backside TSV Revealing and Cu Redistribution Process Enabled by ZoneBOND Temporary Bonding Technology
Lau, Guan Kian
Ding, L.
Tupaen, FlIipona Randy
Ho, G. Q.
PROCEEDINGS OF THE 2013 IEEE 15TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2013), 2013, : 793 - 798
[4] Integration of TSVs, wafer thinning and backside passivation on full 300mm CMOS wafers for 3D applications
Jourdain, Anne
Buisson, Thibault
Phommahaxay, Alain
Redolfi, Augusto
Thangaraju, Sarasvathi
Travaly, Youssef
Beyne, Eric
Swinnen, Bart
2011 IEEE 61ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2011, : 1122 - 1125
[5] Non Conductive Film Analysis Using Cure Kinetics and Rheokinetics for Gang Bonding Process for 3DIC TSV Packaging
Moon, Ji Young
Shin, Yongchul
Kim, Sumin
Hahn, Seung Ho
Lim, Kyeongbin
Jung, Jung Woo
Lim, Chaemook
Kim, Youngbum
Hwang, Jihwan
Rhee, Minwoo Daniel
IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 706 - 710
[6] Key Process Development on 300mm Wafer for 2.5D/3D Integration
Song, Chongshen
Xue, Kai
Jiang, Feng
Li, Hengfu
Feng, Guangjian
Jing, Xiangmeng
Zhang, W.
PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2015, : 241 - 244
[7] Al2O3/InGaAs interface study on MOS capacitors for a 300mm process integration
Billaud, M.
Duvernay, J.
Grampeix, H.
Pelissier, B.
Martin, M.
Baron, T.
Boutry, H.
Chalupa, Z.
Casse, M.
Ernst, T.
Vinet, M.
2015 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2015, : 113 - 116
[8] A high-density logic-on-logic 3DIC design using face-to-face hybrid wafer-bonding on 12nm FinFET process
Sinha, S.
Hung, S.
Fisher, D.
Xu, X.
Chao, C.
Chandupatla, P.
Frederick, F.
Perry, H.
Smith, D.
Cestero, A.
Safran, J.
Ayyavu, V
Bhargava, M.
Mathur, R.
Prasad, D.
Katz, R.
Kinsbruner, A.
Garant, J.
Lubguban, J.
Knickerbocker, S.
Soler, V
Cline, B.
Christy, R.
McLaurin, T.
Robson, N.
Berger, D.
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
[9] 300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications
Rachmady, W.
Agrawal, A.
Sung, S. H.
Dewey, G.
Chouksey, S.
Chu-Kung, B.
Elbaz, G.
Fischer, P.
Huang, C. Y.
Jun, K.
Krist, B.
Metz, M.
Michaelos, T.
Mueller, B.
Oni, A. A.
Paul, R.
Phan, A.
Sears, P.
Talukdar, T.
Torres, J.
Turkot, R.
Wong, L.
Yoo, H. J.
Kavalieros, J.
2019 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2019,
[10] Full 300 mm Electrical Characterization of 3D Integration Using High Aspect Ratio (10:1) Mid-Process Through Silicon Vias
Gaillard, F.
Mourier, T.
Religieux, L.
Bouchu, D.
Ribiere, C.
Minoret, S.
Gottardi, M.
Romero, G.
Mevellec, V.
Aumont, C.
2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC), 2015,

← 1 →