Very Low Bandgap Voltage Reference with High PSRR Enhancement Stage Implemented in 90nm CMOS Process Technology for LDO Application

被引：0
|
作者：
Francisco, Keith R. [1 ]
Hora, Jefferson A. [1 ]
机构：
[1] MSU Iligan Inst Technol, Dept EECE, Microelect Lab, Iligan, Philippines
来源：
IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS DESIGN, SYSTEMS AND APPLICATIONS (ICEDSA 2012) | 2012年
关键词：
Voltage Reference; Low Voltage Bandgap; Low Dropout (LDO) Regulator; Power Supply Rejection Ratio (PSRR);
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low voltage bandgap reference with a high power supply rejection ratio is implemented in TSMC 90nm 1P9M 3.3V CMOS Process Technology. This design can be applied to LDO voltage regulators particularly used in wireless devices and ADC's whose immunity to noise is an essential property. Its power supply rejection ratio is improved by an enhancement stage so as to achieve a high performance analog and digital system which is usually limited by the PSRR of the bandgap reference. The design operates within a range of 2.6 to 3.6 V and has very small temperature and supply sensitivities measuring 6 ppm/degrees C and 20 mu V/V, respectively. The circuit's current consumption is around 127.117 mu A and produces an output voltage of 213.982 mV. The design's PSRR is 82.7 dB and it has a total chip core area of 0.0137 mm(2).
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页码：216 / 220
页数：5
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