A novel fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process

被引：11

作者：

Donkers, J. J. T. M. ^{[1
]}

Kramer, M. C. J. C. M. ^{[1
]}

Van Huylenbroeck, S. ^{[2
]}

Choi, L. J. ^{[2
]}

Meunier-Beillard, P. ^{[1
]}

Sibaja-Hernandez, A. ^{[2
]}

Boccardi, G. ^{[1
]}

van Noort, W. ^{[1
]}

Hurkx, G. A. M. ^{[1
]}

Vanhoucke, T. ^{[1
]}

Vleugels, F. ^{[2
]}

Winderickx, G. ^{[2
]}

Kunnen, E. ^{[2
]}

Peeters, S. ^{[2
]}

Baute, D. ^{[2
]}

De Vos, B. ^{[2
]}

Vandeweyer, T. ^{[2
]}

Loo, R. ^{[2
]}

Venegas, R. ^{[2
]}

Pijper, R. ^{[3
]}

Voogt, F. C. ^{[4
]}

Decoutere, S. ^{[2
]}

Hijzen, E. A. ^{[1
]}

机构：

[1] NXP TSMC Res Ctr, Kapeldreef 75, B-3001 Louvain, Belgium

[2] IMEC, Leuven, Belgium

[3] NXP TSMC Res Ctr, Eindhoven, Netherlands

[4] NXP Semicond, Nijmegen, Netherlands

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4419029

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this architecture is capable of achieving f(T)/f(max) values of 295/425GHz for an effective emitter area of 0.13x5 mu m(2). In this new process approach, which is fully CMOS compatible, the collector and base are grown in a single-step non-selective epitaxial process on top of pre-defined bipolar areas. This provides new opportunities for collector-base profile engineering. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial pedestal defines the intrinsic device and makes Deep Trench Isolation redundant. We describe the major features of the integration scheme and show measured f(T)/f(max) values of 300/220GHz on the first fabricated devices with an effective emitter area of 0.13x5 mu m(2).

引用

页码：655 / +

页数：2

共 7 条

[1] A 400GHz fMAX Fully Self-Aligned SiGe:C HBT Architecture
Van Huylenbroeck, S.
Sibaja-Hernandez, A.
Venegas, R.
You, S.
Winderickx, G.
Radisic, D.
Lee, W.
Ong, P.
Vandeweyer, T.
Nguyen, N. D.
De Meyer, K.
Decoutere, S.
PROCEEDINGS OF THE 2009 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2009, : 5 - +
[2] Integration of a 0.13-μm CMOS and a high performance self-aligned SiGe HBT featuring low base resistance
Hashimoto, T
Nonaka, Y
Saito, T
Sasahara, K
Tominari, T
Sakai, K
Tokunaga, K
Fujiwara, T
Wada, S
Udo, T
Jinbo, T
Washio, K
Hosoe, H
INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, 2002, : 779 - 782
[3] A 0.2-μm self-aligned selective-epitaxial-growth SiGe HBT featuring 107-GHz fmax and 6.7-ps ECL
Washio, K
Kondo, M
Ohue, E
Oda, K
Hayami, R
Tanabe, M
Shimamoto, H
Harada, T
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (09) : 1989 - 1994
[4] Investigation of deep traps in silicon-germanium epitaxial base bipolar transistors with a single polysilicon quasi self-aligned architecture
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Souifi, A
Mouis, M
Chantre, A
Brémond, G
MICROELECTRONICS RELIABILITY, 2001, 41 (02) : 253 - 263
[5] A Novel Approach to Generate Self-aligned Ge/SiO2/SiGe Gate-stacking Structures in a Single Fabrication Step
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Yang, Kuo-Ching
Hsu, Ting-Chia
Liao, Po-Hsiang
George, Thomas
Li, Pei-Wen
2014 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2014,
[6] NOVEL PROCESS FOR EMITTER-BASE-COLLECTOR SELF-ALIGNED HETEROJUNCTION BIPOLAR-TRANSISTOR USING A PATTERN-INVERSION METHOD
TANAKA, S
MADIHIAN, M
TOYOSHIMA, H
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[7] Impact of inside spacer process on fully self-aligned 250 GHz SiGe:C HBTs reliability performances: a-Si vs. nitride
Diop, M.
Revil, N.
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Ghibaudo, G.
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