A High-gain High-precision Dynamic Comparator with Dynamic Cascading Technique

Comparators are widely used in Serializer-Deserializer (SerDes), analog-to-digital converters and so on. A SerDes is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. Transmitter plays a key role in the whole signal transmission system. A good receiver can make up for the shortcomings of the transmitter. Comparator is an important module of receiver. The role of the comparator is to compare the input with the reference signals, and output a logic level as the decision. High precision, high speed, low supply voltage operation, low power consumption, metastability and offset voltage are the critical aspects to be considered while designing CMOS dynamic comparators. In a 28nm CMOS technology, a comparator built by two cascaded pre-amplified dynamic comparators is proposed in this paper. With the presence of cascading, the proposed comparator has high sensitivity and low offset.