A 3.2GS/s 4.55b ENOB Two-Step Subranging ADC in 45nm SOI CMOS

被引：0
|
作者：
Plouchart, J. -O. [1 ]
Sanduleanu, M. A. T. [1 ]
Toprak-Deniz, Z. [1 ]
Beukema, T. J. [1 ]
Reynolds, S. [1 ]
Parker, B. D. [1 ]
Beakes, M. [1 ]
Tierno, J. A. [1 ]
Friedman, D. [1 ]
机构：
[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY USA
来源：
2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2012年
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D O I：
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 3.2GS/s two-step subranging ADC is implemented in a 45nm SOI-CMOS technology. The measured ENOB is 4.55b at 1.6GHz. The IIP3 is -1.1dBm. The power consumption is 22mW from a 1.05V voltage supply for a FOM of 290fJ/ conversion-step. The chip occupies an active area of 0.07mm(2).
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页数：4
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