Expendable modular chips for feedforward neural nets

被引：0
|
作者：
Cho, HH [1 ]
Kim, HC [1 ]
Choi, MR [1 ]
机构：
[1] Hanyang Univ, ASIC Lab, Dept EECI, Seongdong Ku, Seoul 133791, South Korea
来源：
8TH INTERNATIONAL CONFERENCE ON NEURAL INFORMATION PROCESSING, VOLS 1-3, PROCEEDING | 2001年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Simple nonlinear synapse circuit proposes for implementation of artificial neural networks using standard CMOS technology. The operation of the proposed synapse circuit has been verified using HSPICE circuit simulator. A 9x3 module chip has been designed and fabricating using MOSIS AMI 1.5 mum double-metal double-poly CMOS process. The modular neural chip might be very suitable for the future implementation of the large-scale neural networks with on-chip learning.
引用
收藏
页码：1211 / 1213
页数：3
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