Soft Error Vulnerability Assessment of the Real-Time Safety-Related ARM Cortex-R5 CPU

被引:0
|
作者
Iturbe, Xabier [1 ]
Venu, Balaji [1 ]
Ozer, Emre [1 ]
机构
[1] ARM Res, Cambridge, England
关键词
UPSET;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the results collected in a series of fault injection experiments conducted on a modern commercial embedded ARM Cortex-R5 processor, which is extensively used in real-time safety-related embedded applications. The paper aims to be a comprehensible study on how faults propagate through this CPU as they turn into errors at the core boundaries. The main goal of this study is to identify the most vulnerable parts in the micro-architecture of the ARM Cortex-R5 CPU. The long-term objective is to propose and decide how to protect these vulnerable parts without impacting the characteristic features of ARM processors: energy-efficiency and high-performance.
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页码:91 / 96
页数:6
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    [J]. REAL-TIME SYSTEMS EDUCATION, 1996, : 98 - 107
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    [J]. TWENTY-EIGHTH ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, DIGEST PAPERS, 1998, : 402 - 407
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