Using run-time reconfiguration for fault injection applications

被引:0
|
作者
Antoni, L [1 ]
Leveugle, R [1 ]
Fehér, B [1 ]
机构
[1] Inst Natl Polytech Grenoble, TIMA, Lab Tech Informat & Microelect Comp Architecture, F-38031 Grenoble, France
关键词
fault-injection; Partial Run-Time Reconfiguration; FPGA;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, approaches using Run-Time Reconfiguration for fault injection in programmable systems are introduced. In FPGA-based systems an important characteristic is the time to reconfigure the hardware, including re-synthesis, place and route and finally bitstream downloading. Modifications can be carried out at "low-level", directly in the bitstream, so that re-synthesizing the description can be avoided to inject new faults. Moreover, with some FPGA families (e.g. Virtex or AT6000), it is possible to reconfigure the hardware partially at run-time. Important time-savings can be achieved when taking advantage of these features. These characteristics fit well to apply with fault injection where the injection necessitates the reconfiguration of only a few resources of the device with a few modifications. Time gains can be various depending on the number and kind of faults to be injected and the device used for the experiments. The experiments show that his approach could be several orders faster than the implementation using Compile-Time Reconfiguration.
引用
收藏
页码:1773 / 1777
页数:5
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