A Noise-Shaping SAR ADC with Dual Error-Feedback Paths and Alternate DACs

This paper presents an opamp-free solution to implement noise-shaping technique in successive-approximation register (SAR) ADCs. With delayed quantization error applied to both comparator and sample-hold circuit through dual feedback paths, effective noise-shaping is achieved using a passive loop filter. Two identical switched-capacitors DACs are employed to perform voltage approximation and to maintain the quantization error alternately. A SAR ADC adopting the proposed opamp-free noise-shaping solution is designed in a 0.18-mu m CMOS process. Post-layout simulation exhibits 10.6-bit accuracy at 48MS/s sampling frequency based on 8-bit DAC when the oversampling rate is 4. The proposed ADC dissipates 451 W from a 1.5-V supply and achieves a Walden FOM of 24.2 fJ/conversion-step.