Single mode Quasi-cyclic LDPC Decoder Using Modified Belief Propagation

被引：0

作者：

Mankar, Monica V. ^{[1
]}

Patil, Abha ^{[1
]}

Asutkar, G. M. ^{[2
]}

机构：

[1] Rashtrasant Tukadoji Maharaj Nagpur Univ, Dept Elect Engn, Yeshwantrao Chavan Coll Engn, Nagpur, Maharashtra, India

[2] Rashtrasant Tukadoji Maharaj Nagpur Univ, Dept Elect & Commun Engn, Priyadarshini Inst Engn & Technol, Nagpur, Maharashtra, India

来源：

2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP) | 2014年

关键词：

Belief propagation algorithm; LDPC codes; QC-LDPC; Single mode decoder;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low Density Parity Check codes (LDPC) have shown good error correcting performance which enables efficient and reliable communication. A subclass of LDPC codes known as quasi-cyclic LDPC codes are used whose parity check matrices consists of circulant permutation matrices. QC-LDPC codes require less memory as compared to LDPC codes. This paper presents a low complexity quasi-cyclic low density parity check (QC-LDPC) decoder. QC-LDPC codes require less memory as compared to LDPC codes. Partially parallel, low complexity decoder architecture has been designed for single-mode decoding. This decoder is modeled in Verilog, synthesized and performed place and route for the design using Xilinx ISE 12.1.

引用

页数：5

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