Efficient Fast Convolution Architectures for Convolutional Neural Network

被引:0
|
作者
Xu, Weihong [1 ,2 ]
Wang, Zhongfeng [3 ]
You, Xiaohu [2 ]
Zhang, Chuan [1 ,2 ]
机构
[1] Lab Efficient Architectures Digital Commun & Sign, Nanjing, Jiangsu, Peoples R China
[2] Southeast Univ, Natl Mobile Commun Res Lab, Nanjing, Jiangsu, Peoples R China
[3] Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China
关键词
Fast convolution; parallel processing; data reuse; hardware reconfigurability; convolutional neural network (CNN);
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Due to the world-wide interests on artificial intelligence, many acceleration architectures for convolutional neural network (CNN) have been proposed recently. However, few of them focus on reducing convolution computation strength. In this paper, we first present fast convolution algorithm and its matrix form. Then based on the fast convolution algorithm, a fully parallel architecture with high throughput is proposed. To further increase efficiency and reduce computation redundancy, output data reuse scheme corresponding to CNN is also considered by introducing affordable adders and buffers. The hardware implementation and complexity comparison are conducted among different convolution architectures. Implementation results on Zynq XC7Z045 platform demonstrate the effectiveness of proposed fast convolution architectures in the reduction of complexity. Compared to conventional 2-D convolver, our 3 parallel fast convolution filter reduces 28% hardware resources and improves throughput by 17%. After deploying data reuse scheme, our fast convolution architecture is 10.56x faster.
引用
收藏
页码:904 / 907
页数:4
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