Correlation between SET-State Current Level and Read Disturb Failure Time in a Resistive Switching Memory

被引:0
|
作者
Su, P. C. [1 ]
Jiang, C. M. [1 ]
Wang, C. W. [1 ]
Wang, Tahui [1 ]
机构
[1] Natl Chiao Tung Univ, Inst Elect, Hsinchu, Taiwan
关键词
RRAM; read-disturb failure; SET-state current level; model;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The relationship between SET-state current level and read-disturb failure time in a tungsten oxide RRAM is characterized and modeled. Our result shows that read voltage induced reduction of oxygen vacancy density in tungsten oxide follows a power law dependence on cumulative read-disturb time. The power factor is independent of SET-state current level. Read disturb failure time is considerably improved by several orders of magnitude as SET-state current level increases a few times. An analytical model to correlate SET-state current level and read disturb failure time is proposed. Since SET-state current level is related to a cross-section of a conductive filament in an oxide, our model is developed based on a relationship between oxide area and critical oxide trap (oxygen vacancy) density from an oxide breakdown model. The validity of the proposed model is supported by experiment results.
引用
收藏
页数:5
相关论文
共 27 条
  • [1] Modeling of Read-Disturb-Induced SET-State Current Degradation in a Tungsten Oxide Resistive Switching Memory
    Su, Po-Cheng
    Jiang, Cheng-Min
    Wang, Chih-Wei
    Wang, Tahui
    IEEE ELECTRON DEVICE LETTERS, 2018, 39 (11) : 1648 - 1651
  • [2] Characterization and modeling of SET/RESET cycling induced read-disturb failure time degradation in a resistive switching memory
    Su, Po-Cheng
    Hsu, Chun-Chi
    Du, Sin-I
    Wang, Tahui
    JOURNAL OF APPLIED PHYSICS, 2017, 122 (21)
  • [3] Investigation of Factors Affecting SET-Disturb Failure Time in a Resistive Switching Memory
    Su, P. C.
    Chung, Y. T.
    Chen, M. C.
    Wang, Tahui
    2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2016,
  • [4] Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory
    Chung, Yueh-Ting
    Su, Po-Cheng
    Cheng, Yu-Hsuan
    Wang, Tahui
    Chen, Min-Cheng
    Lu, Chih-Yuan
    IEEE ELECTRON DEVICE LETTERS, 2015, 36 (02) : 135 - 137
  • [5] An Analytical Model of Read-Disturb Failure Time in a Post-Cycling Resistive Switching Memory
    Jiang, Cheng-Min
    Wang, Chih-Chieh
    Li, Kai-Shin
    Lin, Chao-Cheng
    Wang, Tahui
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2021, 21 (04) : 603 - 607
  • [6] SET/RESET Cycling-Induced Trap Creation and SET-Disturb Failure Time Degradation in a Resistive-Switching Memory
    Chung, Yueh-Ting
    Su, Po-Cheng
    Lin, Wen-Jie
    Chen, Min-Cheng
    Wang, Tahui
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2016, 63 (06) : 2367 - 2373
  • [7] Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
    Su, Po-Cheng
    Jiang, Cheng-Min
    Chen, Yu-Jia
    Wang, Chih-Chieh
    Li, Kai-Shin
    Lin, Chao-Cheng
    Wang, Tahui
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (01) : 113 - 117
  • [8] Identification of the controlling parameter for the set-state resistance of a TiO2 resistive switching cell
    Song, Seul Ji
    Kim, Kyung Min
    Kim, Gun Hwan
    Lee, Min Hwan
    Seok, Jun Yeong
    Jung, Ranju
    Hwang, Cheol Seong
    APPLIED PHYSICS LETTERS, 2010, 96 (11)
  • [9] The Statistics of Set Time of Oxide-based Resistive Switching Memory
    Zhang, Meiyun
    Long, Shibing
    Wang, Guoming
    Yu, Zhaoan
    Li, Yang
    Xu, Dinglin
    Lv, Hangbing
    Liu, Qi
    Miranda, Enrique
    Sune, Jordi
    Liu, Ming
    PROCEEDINGS OF THE 2016 IEEE 23RD INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2016, : 392 - 394
  • [10] Self-compliance SET switching and multilevel TaOx resistive memory by current-sweep operation
    Li, M. H.
    Jiang, Y.
    Zhuo, V. Y. -Q.
    Yeo, E. -G.
    Law, L. -T.
    Lim, K. -G.
    2014 14TH ANNUAL NON-VOLATILE MEMORY TECHNOLOGY SYMPOSIUM (NVMTS), 2014,