AUTOMATIC GENERATION OF RANDOM STIMULI SOURCES BASED ON PARAMETER DOMAINS FOR FUNCTIONAL VERIFICATION

Functional verification is based on the simulation of a circuit's hardware design language (HDL) model at register transfer level (RTL) and checking the results against the specification. Random stimuli generation has been largely used in different testbench architectures, but the manual coding of the stimuli sources may lead to the stimulation of redundant and invalid test vectors what causes a negative impact on verification performance. They can be eliminated by taking advantage of the dependencies of design's input parameters, splitting the simulation space into Parameter Domains. In this paper we propose an efficient functional verification methodology based on the Parameter Domains framework and constraint based random stimulation. Additionally, the paper presents a tool to automatically generate SystemC stimuli sources from module's parameter domains specification, providing an extra verification time save-up.