A Low-jitter 1.5-GHz and 350-ppm Spread-spectrum Serial ATA PHY Using Reference Clock with 400-ppm Production-frequency Tolerance

A serial ATA PHY was fabricated in a 0.15-mu m CMOS process with a technique of calibrating a spread spectrum clock generator (SSCG). This technique involves calibrating the SSCG output signal frequency, which does not meet the serial-ATA specifications due to large variations in the reference oscillator, by utilizing the received signal during a power-on sequence. This is achieved by shifting the SSCG divide ratio, which is the input signal of the Sigma Delta modulator. A feed-forward delay cell and voltage to the current converter with a high current limiter are applied to a VCO to achieve low jitter and prevent the SSCG from malfunctioning. This technique enables a serial ATA PHY to use reference oscillators with a production-frequency tolerance of less than 400 ppm, i.e., higher than the permissible TX frequency variations (i.e., 350 ppm). The calibrated SSCG achieved a total jitter of 3.9 ps.