Transfer characteristic shift technique for full input range in pipelined ADCs with background calibration

A transfer characteristic shift technique has been proposed in this paper. By shifting the transfer characteristic of the sub-stage under calibration in pipelined ADC, a full input range is realized for pipelined ADC with background calibration. Pseudorandom sequence (PN) signal with maximum amplitude of Vref/4 can be injected into the multiplying digital-to-analog converter (MDAC) which speeds up the convergence process. Simulation results shows that the technique can achieve full input range and fast convergence speed simultaneously with small hardware cost in pipelined ADCs with PN signal based background calibration.