Analysis and Implementation of Parallel Causal Bit Plane Coding In JPEG2000 Standard

被引:0
|
作者
Ghodhbani, Refka [1 ]
Saidani, Taoufik [1 ]
Horrigue, Layla [1 ]
Atri, Mohamed [1 ]
机构
[1] Univ Monastir, Fac Sci, Elect & Microelect Lab, Monastir, Tunisia
关键词
EBCOT; JPEG2000; VHDL; FPGA; VLSI; ARCHITECTURE;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
With the augmentation in multimedia technology, demand for high speed real time image compression system has also increased. JPEG2000 is a relatively new image compression standard which builds and improves on its predecessor JPEG. In Jpeg 2000 the embedded Block Coding with Optimal Truncation (EBCOT) is the most important element to calculate the very hard portion in the compressing process of JPEG 2000 image compression standard. This paper proposes a Parallel Bit Plane Coding (BPC) architecture in which three coding passes operate in parallel and are allowed to progress independently. The proposed architecture with causal mode is able to benefit 3/4 of clock cycles than a parallel coder with normal mode.
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页数:6
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