An AOCA-Based VLSI architecture for non-recursive 2D discrete periodized wavelet transform

All traditional VLSI architectures of the 2D discrete wavelet transform (DWT) are based on the recursive pyramid algorithm. They need interleaving technique to solve the confliction problem of multi-level input data. This increases circuit complexity and time latency as the decomposition stage is increased. Instead, this paper presents a non-recursive algorithm of the separable 2D DPWT, by which each stage's decomposition can be performed independently and the 2D DPWT coefficients of all stages can be obtained simultaneously. Based on the AOCA process, an efficient process called segment accumulation algorithm (SAA) is proposed to overcome the filter growing problem, With the property of using the same original data for all stages, data sharing technique can be applied in the parallel processing scheme of the SAA for circuit complexity reduction. The SAA provides three fundamental ID DPWT VLSI architectures with the advantages of requiring no multiplex, less multiplier, adder, and non-interleaving process. Moreover, the latency of the architecture is independent of the decomposition levels and can be very short.