A performance optimized CMOS distributed LNA for UWB receivers

This paper presents the design and implementation of a performance-optimized LNA circuit targeted for UWB receivers. The systematic design of a CMOS distributed LNA circuit comprising cascode cells will be illustrated. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the bandwidth, while reducing the high-frequency input-referred noise. A three-stage performance optimized LNA has been fabricated in Jazz's sbc18 0.18 mu m SiGe process, while using MOS transistors only. Measurements of the LNA circuit show a 2.9-dB noise figure and a forward gain of 8dB over the 7.5GUz UWB bandwidth. The circuit exhibits an IIP3 of -3.4dBm.