Rail-to-rail input/output operational transconductance amplifier (OTA) with high CMRR and PSRR

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance (G (m)), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With +/- 0.75 v power supply, this OTA consumes the low power of 397.5 mu w. G (m) variation of input stage is 0.004% for rail-to-rail (+/- 0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (+/- 1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is -46 dB for 2.15 v(P-P) differential output voltage signal with applying a 0.48 v(P-P) input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 mu m CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process.