A new CD measurement method linked with the electrical properties of devices

This paper describes a new measurement method of a CD-SEM with nanometer-level precision and good correlation with electrical characteristics for an actual device of ultra-large-scale integration (ULSI). With the decrease in feature size, the pattern to be measured tends to become a curved shape. In order to measure such a pattern within measurement precision on the order of 5 nm, two-dimensional measurement is effective. Here we report a new measurement algorithm featuring that the critical dimension is derived from the value of the area of a measurement pattern. We apply this measurement method to actual device of 64-Mbit DRAM and confirm the reproducibility of 3.6 nm for the gate linewidth measurement, and that of 5.6 nm for the hole diameter measurement. Furthermore, we verify that the measurement values of the gate linewidth have a strong correlation with the threshold voltage and those of the hole diameter also have a strong correlation with the contact resistance, respectively.