Suppression of MOSFET reverse short channel effect by channel doping through gate electrode

The purpose of this paper is to suppress the reverse short channel effect (RSCE) of 0.18 mum CMOS, which leads to the increase of standby current in the PLL and the output buffer circuits. RSCE is owing to the transient enhanced diffusion of the channel profile induced by source/drain (SID) implantation. We propose the new process in which the boron for nMOS threshold voltage (V-th) adjustment is implanted through the gate electrode after SID activation annealing over the blanket of wafer. It enables nMOS transistor to have less than 0.1V V-th roll-up without increasing wafer cost, It can also effectively apply in the case of less than 0.13 mum devices, not being limited in the case of 0.18 mum CMOS devices.