Probabilistic Replacement Strategies for Improving the Lifetimes of NVM-Based Caches

Non-volatile memory (NVM) technologies present an opportunity to improve area efficiency and reduce energy consumption throughout the memory hierarchy. However, write endurance can hinder the adoption of NVM in lower-level caches. With an estimated write endurance of one trillion write cycles, Spin-Torque Transfer RAM (STT-RAM) is a more likely candidate for application as an L2 cache than Resistive RAM (ReRAM) or Phase-Change Memory (PCM). In resource-constrained systems where aggressive wear-leveling techniques cannot be applied, light-weight alternatives may be necessary to extend the lifetime of the cache. In this paper, we propose and evaluate a hybrid-random replacement policy as a low-overhead approach to wear-leveling to improve the lifetime of a large non-volatile memory L2 cache. We investigate another probabilistic mechanism that utilizes approximate counters as an alternative method of injecting random events in the eviction stream. We show that our hybrid-random policy extends the lifetime of an NVM L2 cache by 0.5 to 16 years across many benchmarks over an LRU-replacement baseline. Our approximate counter approach further extends the lifetime by 1.7 to 19 years over the baseline but incurs a higher overhead.