A 9-11-Bit Phase-Interpolating Digital Pulsewidth Modulator With 1000x Frequency Range

被引：9

作者：

Lee, Yoontaek ^{[1
,2
]}

Kang, Taewook ^{[1
,2
]}

Kim, Jaeha ^{[1
,2
]}

机构：

[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul 151742, South Korea

[2] Seoul Natl Univ, Interuniv Semicond Res Ctr, Seoul 151742, South Korea

来源：

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS | 2015年 / 51卷 / 04期

基金：

新加坡国家研究基金会;

关键词：

Digital control; mixed analog digital integrated circuits (ICs); power system control; programmable control; pulsewidth modulation; DC-DC CONVERTERS; CMOS; CIRCUIT; ARRAYS; DPWM;

D O I：

10.1109/TIA.2015.2411656

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A design of a new hybrid-type digital pulsewidth modulator (DPWM) with a wide frequency range of 1000 : 1, from 10 kHz to 10 MHz, is presented. The proposed DPWM has the maximum duty-cycle resolution of 11 bits and consumes the power of 17.5 mu W at 10 kHz and 2.36 mW at 10 MHz, respectively. The proposed DPWM realizes the upper 5-bit resolution using a programmable digital counter and the lower 6-bit resolution using a current-integrating-type phase interpolator, employing an M2M-ladder current-steering digital-to-analog converter for low power consumption. The operating clock is generated in on-chip using a relaxation oscillator. The prototype integrated circuit fabricated in a 0.25-mu m high-voltage complementary metal-oxide-semiconductor demonstrates that the proposed DPWM maintains a good linearity across the entire operating range.

引用

页码：3376 / 3384

页数：9