Real-time Implementation of Chirp Scaling Algorithm

Echo data generated by Synthetic aperture radar (SAR) has the characteristics of high data rate and huge data quantity. However, the complex Chirp Scaling (CS) algorithm in SAR processing leads to excessive calculations. To solve this problem, this paper presents an implementation on a parallel structure real-time image processing board, which adopts principal-subordinate parallel processing structures. The principal FPGA board is responsible for the control of the entire image processing, data collection, distribution and interaction. Each subordinate FPGA, as an independent processing unit, is able to independently finish the FFT transformation and phase factor compensation. The performance of the high-performance parallel FFT processors is 4 times as efficient as that of a single butterfly processor. The phase factor generation and compensation is optimized through two steps, one is fast algorithm in phase factor generation and compensation; the other is the optimization among the processing procedures,The proposed architecture can process an image in size16384 x 65536 at 100MHZ operation frequency within 12.5s.