A Coarse-grained Asynchronous Data-Driven Design Flow

被引：0
|
作者：
Ren, Hongguang [1 ]
Wang, Zhiying [1 ]
Lu, Hongyi [1 ]
机构：
[1] Natl Univ Def Technol, Sch Comp, Changsha 410073, Hunan, Peoples R China
来源：
2011 INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND NETWORK TECHNOLOGY (ICCSNT), VOLS 1-4 | 2012年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
As the synchronous circuit design is facing some limits, such as the power wall and the clock skew problem, the asynchronous circuit design is approaching a revival. This paper presents a coarse-grained data-driven design flow for asynchronous circuits, which aims at both performance and design efficiency. Based on a set of data-driven components, pipelined asynchronous circuits can be efficiently constructed. We optimize the circuits by combining components to form coarse-grained pipelines. Experimental results on an asynchronous pipelined 32-bit iterative multiplier show the efficiency of our design flow.
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收藏
页码：2602 / 2605
页数：4
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