Parallel memory architecture for arbitrary stride accesses

被引：0
|
作者：
Aho, Eero [1 ]
Vanne, Jarno [1 ]
Hamalainen, Timo D. [1 ]
机构：
[1] Tampere Univ Technol, Inst Digital & Comp Syst, Tampere, Finland
来源：
PROCEEDINGS OF THE 2006 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2006年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory architecture allows conflict free accesses with all the constant strides which has not been possible In prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the data patterns have equal amount of accessed data elements as the number of memory modules. The complexity is evaluated with resource counts.
引用
收藏
页码：65 / +
页数：2
相关论文
共 50 条
  • [1] Parallel memory implementation for arbitrary stride accesses
    Aho, Eero
    Vanne, Jarno
    Hamalainen, Timo D.
    [J]. 2006 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION, PROCEEDINGS, 2006, : 1 - +
  • [2] Memory Organization with Multi-Pattern Parallel Accesses
    Vitkovski, Arseni
    Kumanov, Georgi
    Gaydadjiev, Georgi
    [J]. 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1224 - +
  • [3] Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
    Paulino, Nuno
    Ferreira, Joao Canas
    Cardoso, Joao M. P.
    [J]. RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, 2013, 7806 : 122 - 133
  • [4] A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
    Paulino, Nuno
    Ferreira, Joao Canas
    Cardoso, Joao M. P.
    [J]. ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2015, 7 (04)
  • [5] Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs
    Nabi, Syed Waqar
    Vanderbauwhede, Wim
    [J]. 2019 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW), 2019, : 87 - 90
  • [6] BLOCK, MULTISTRIDE VECTOR, AND FFT ACCESSES IN PARALLEL MEMORY-SYSTEMS
    HARPER, DT
    [J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 1991, 2 (01) : 43 - 51
  • [7] Supporting small accesses for the parallel file subsystem on Distributed Shared Memory systems
    Liu, YZ
    Mac, SC
    Shieh, CK
    [J]. 1998 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS, PROCEEDINGS, 1998, : 808 - 815
  • [8] A memory Mapping Approach for Parallel Interleaver design with multiples read and write accesses
    Chavet, C.
    Coussy, P.
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 3168 - 3171
  • [9] Parallel divider for architecture numbers of arbitrary word length
    Nakamura, Tsugio
    Kasahara, Hiroshi
    [J]. Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 1992, 75 (12): : 57 - 66
  • [10] A parallel memory architecture for video coding
    Jian-ying Peng
    Xiao-lang Yan
    De-xian Li
    Li-zhong Chen
    [J]. Journal of Zhejiang University-SCIENCE A, 2008, 9 : 1644 - 1655
12345