Origin of hysteresis in current-voltage characteristics of polycrystalline silicon thin-film transistors

被引：22
|
作者：
Lin, Horng-Chih [1 ,2 ,3 ]
Hung, Cheng-Hsiung [2 ,3 ]
Chen, Wei-Chen [2 ,3 ]
Lin, Zer-Ming [2 ,3 ]
Hsu, Hsing-Hui [2 ,3 ]
Hunag, Tiao-Yuang [2 ,3 ]
机构：
[1] Natl Nano Device Labs, Hsinchu 300, Taiwan
[2] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
[3] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan
来源：
JOURNAL OF APPLIED PHYSICS | 2009年 / 105卷 / 05期
关键词：
deep levels; defect states; electron traps; elemental semiconductors; grain boundaries; hysteresis; interface states; silicon; thin film transistors; GAP-STATE DENSITY; MECHANISM;
D O I：
10.1063/1.3086271
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
In this work we report the observation and characterization of a hysteresis phenomenon in the transfer characteristics of n-channel polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Such phenomenon is observed in devices with fully depleted channel and not treated with hydrogen-related anneal. The origin of the hysteresis is identified to be related to the electron trapping and detrapping processes associated with the deep-level traps in the grain boundaries of the poly-Si channel.
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页数：6
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