Electrical stress in CdS thin film transistors using HfO2 gate dielectric

被引：11

作者：

Garcia, R. ^{[1
]}

Mejia, I. ^{[2
]}

Molinar-Solis, J. E. ^{[1
]}

Salas-Villasenor, A. L. ^{[2
]}

Morales, A. ^{[1
]}

Garcia, B. ^{[1
]}

Quevedo-Lopez, M. A. ^{[2
]}

Aleman, M. ^{[3
]}

机构：

[1] Univ Autonoma Estado Mexico, Ctr Univ Ecatepec, Ecatepec 55020, Uaemex, Mexico

[2] Univ Texas Dallas, Dept Mat Sci & Engn, Richardson, TX 75083 USA

[3] IPN, Ctr Nanociencias & Micro & Nanotcnol, Mexico City 07738, DF, Mexico

来源：

APPLIED PHYSICS LETTERS | 2013年 / 102卷 / 20期

关键词：

BIAS STRESS; TFT; DEGRADATION; MOBILITY;

D O I：

10.1063/1.4807720

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, I-on/I-off ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve. (C) 2013 AIP Publishing LLC.

引用

页数：4

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