System-Level Modelling of Dynamic Reconfigurable Designs using Functional Programming Abstractions

被引：0
|
作者：
Uchevler, B. N.
Svarstad, Kjetil
Kuper, Jan
Baaij, Christiaan
机构：
来源：
PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) | 2013年
关键词：
Run-Time Reconfiguration; Self-Reconfiguration; Functional HDL; Partial Evaluation;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.
引用
收藏
页码：379 / 385
页数：7
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