Testing of Asynchronous Circuit using Time Petri-Net Specification

This paper proposes a testing technique for asynchronous circuits using Time Petri-Net Specifications in order to investigate stuck-at faults. This novel technique assumes that a circuit may be tested by only applying a small set of necessary test patterns obtained from the specifications. The main contribution of the paper is the abstraction of the patterns derived from TPN specifications. The four-phase control circuits used as examples show that our approach generates test vectors that can determine the faulty behavior of asynchronous circuits.