Intrinsic Transistor Reliability Improvements from 22nm Tri-Gate Technology

被引：0

作者：

Ramey, S. ^{[1
]}

Ashutosh, A. ^{[2
]}

Auth, C. ^{[2
]}

Clifford, J. ^{[2
]}

Hattendorf, M. ^{[2
]}

Hicks, J. ^{[1
]}

James, R. ^{[2
]}

Rahman, A. ^{[1
]}

Sharma, V. ^{[2
]}

St Amour, A. ^{[2
]}

Wiegand, C. ^{[2
]}

机构：

[1] Intel Corp, Log Technol Dev Qual & Reliabil, Hillsboro, OR 97124 USA

[2] Intel Corp, Portland Technol Dev, Hillsboro, OR USA

来源：

2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2013年

关键词：

BTI; TDDB; HCI; reliability; FinFET; tri-gate;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper highlights the intrinsic reliability capabilities of Intel's 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-kappa/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

引用

页数：5

共 50 条

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