Hardware implementation of fast division algorithm for GF(2m)

被引：0

作者：

Kang, MS ^{[1
]}

Lee, KH ^{[1
]}

机构：

[1] Anyang Univ, Dept Comp Engn, Anyang 430714, Kyonggi, South Korea

来源：

8TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY, VOLS 1-3: TOWARD THE ERA OF UBIQUITOUS NETWORKS AND SOCIETIES | 2006年

关键词：

binary extended GCD algorithm; Finite field arithmetic; Euclidean algorithm; modular division; FPGA;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a fast division algorithm and architecture for GF(2(m)) using standard basis representation. The algorithm implemented is based on the binary Extended GCD algorithm. We have shown that the computation speed of the proposed algorithm is significantly improved than the previous approach. The design can operate at a clock frequency of 80 MHz on Xilinx-VirtexII XC2V8000 FPGA device.

引用

页码：U117 / U119

页数：3

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