FPGA-Based Real-time Interference Alignment Verification System

被引：0
|
作者：
Sun, Zhixin [1 ,2 ]
Zhang, Shun [1 ]
Li, Hongyan [1 ]
Cui, Tingting [1 ]
Qiu, Hao [1 ]
机构：
[1] Xidian Univ, State Key Lab Integrated Serv Networks, Xian 710071, Shaanxi, Peoples R China
[2] Sci & Technol Commun Networks Lab, Shijiazhuang 050081, Hebei, Peoples R China
来源：
2018 IEEE/CIC INTERNATIONAL CONFERENCE ON COMMUNICATIONS IN CHINA (ICCC) | 2018年
基金：
中国国家自然科学基金;
关键词：
Interference alignment; verification system; software defined radio; FPGA; HDL; modular design;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We propose a FPGA-based real-time interference alignment (IA) verification system by combining multiple FPGA from a software defined radio (SDR), where the highlevel hardware description language (HDL) and the modular design are adopted. The system exhibits excellent scalability, utility and flexibility in the development of the IA verification system, and reduces the computational amount and complexity of implementing IA technology. Referring to IEEE 802.11a physical protocol data unit (PPDU) frame structure, this paper designs a unique physical frame structure to obtain the global channel status information (CSI). To demonstrating the IA verification system, this paper detailed describes the accomplished procedure based on the proposed system architecture at SDR.
引用
收藏
页码：656 / 660
页数：5
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