A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem

被引：0

作者：

Wu, CH ^{[1
]}

Shieh, MD ^{[1
]}

Wu, CH ^{[1
]}

Sheu, MH ^{[1
]}

Sheu, JL ^{[1
]}

机构：

[1] Natl Yunlin Univ Sci & Technol, Dept Elect Engn, Touliu, Yunlin, Taiwan

来源：

ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI | 1999年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a high-radix modular multiplication algorithm and its corresponding VLSI architecture for RSA cryptosystem. To reduce the total number of required operations, we partition the multiplier operand into several equal-sized segments and treat each segment as a basic unit for accumulation and module operations. Then, the multiplication and residue calculation of each segment are performed in a pipelined fashion to increase the throughput rate. This paper also shows how to simplify the quotient estimation based on multiple-bit overlapping scanning and to reduce the logic depth in high-radix implementation. Results show that only a small lookup table is needed for quotient estimation in our development and the total operating time is smaller than that of the corresponding radix-2 implementation.

引用

页码：500 / 503

页数：4

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