共 31 条
- [1] An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network [J]. 2024 25TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED 2024, 2024,
- [2] IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network [J]. 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2018, : 111 - 116
- [4] A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks [J]. 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2019, : 166 - 167
- [5] An Energy-efficient Matrix Multiplication Accelerator by Distributed In-memory Computing on Binary RRAM Crossbar [J]. 2016 21ST ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2016, : 280 - 285
- [6] Energy-Efficient In-Memory Binary Neural Network Accelerator Design Based on 8T2C SRAM Cell [J]. IEEE SOLID-STATE CIRCUITS LETTERS, 2022, 5 : 70 - 73
- [7] IMC: Energy-Efficient In-Memory Convolver for Accelerating Binarized Deep Neural Network [J]. PROCEEDINGS OF NEUROMORPHIC COMPUTING SYMPOSIUM (NCS 2017), 2017,
- [8] High Performance and Energy-Efficient In-Memory Computing Architecture based on SOT-MRAM [J]. PROCEEDINGS OF THE IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES (NANOARCH 2017), 2017, : 97 - 102
- [9] 2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning [J]. IEEE SOLID-STATE CIRCUITS LETTERS, 2020, 3 : 194 - 197