On C-testability of carry free dividers

被引：0

作者：

Aziz, SM ^{[1
]}

Carr, SJ ^{[1
]}

机构：

[1] Univ S Australia, Sch Elect & Informat Engn, Adelaide, SA 5095, Australia

来源：

FIRST IEEE INTERNATION WORKSHOP ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS | 2002年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper examines the C-testability of a carry free divider architecture that uses a radix-2 number system. This divider is extremely fast in comparison to the traditional carry-propagate method of division. It has a computational time of the order of O(W), while carry-propagate division has a time of the order of O(W-2). The results of the investigation presented here show that the architecture requires the addition of a significant amount of logic circuits, for correct functionality, and uniformity of the inputs and outputs. This paper presents the logic blocks required to turn the architecture into one that cart be implemented in hardware and examines the effects of these changes on the computation time and testability.

引用

页码：417 / 421

页数：5

共 50 条

[1] The C-testability analyze of the SuperBlock carry-lookahead adder (SBCLA)
Popescu, DE
Popescu, C
2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2002, : 469 - 472
[2] ON THE C-TESTABILITY OF GENERALIZED COUNTERS
CHATTERJEE, A
ABRAHAM, JA
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (05) : 713 - 726
[3] ON THE C-TESTABILITY OF GENERALIZED COUNTERS.
Chatterjee, Abhijit
Abraham, Jacob A.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986, CAD-6 (05)
[4] C-TESTABILITY OF TWO-DIMENSIONAL ITERATIVE ARRAYS
ELHUNI, H
VERGIS, A
KINNEY, L
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1986, 5 (04) : 573 - 581
[5] C-TESTABILITY OF 2-DIMENSIONAL SEQUENTIAL ARRAYS
HUANG, WK
LOMBARDI, F
INTERNATIONAL JOURNAL OF ELECTRONICS, 1990, 69 (05) : 681 - 689
[6] A C-TESTABILITY APPROACH FOR TWO-DIMENSIONAL ITERATIVE ARRAYS
HUANG, WK
LOMBARDI, F
INTERNATIONAL JOURNAL OF ELECTRONICS, 1988, 64 (02) : 179 - 197
[7] DESIGN AND TEST-GENERATION OF C-TESTABLE HIGH-SPEED CARRY-FREE DIVIDERS
WEY, CL
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1995, 142 (03): : 193 - 200
[8] Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays
Chakraborty, A
18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS, 2005, : 249 - 254
[9] Testability synthesis for jumping carry adders
Chen, CIH
Wagh, M
VLSI DESIGN, 2002, 14 (02) : 155 - 169
[10] CONCURRENT-ERROR DETECTION IN HIGH-SPEED CARRY-FREE DIVIDERS
WEY, CL
BERTHELOT, N
VELTKAMP, B
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1994, 141 (06): : 356 - 360

← 1 2 3 4 5 →