Energy-and Performance-Aware Router Design for Chip Multiprocessors

On-chip interconnection networks simplify the challenges of integrating a large number of processing cores. Routers are the backbone of networks. Buffers in router consume significant area and power of the network. Reducing buffers could lead to degradation of network performance. Dual crossbar router architecture combines buffered and bufferless feature to reduce buffer read/write energy. Marching memory buffers achieve high-speed operation with a low power consumption. Switch folding technique is used to reduce wire density and decrease muxes in crossbar. In this paper, we propose Folded Dual Crossbar with Marching memory based buffer (FDCM) router architecture by combining the Dual crossbar, Marching memory, and Folding technique in order to get advantages of these architectures. Simulation results show that there is significant improvement in energy and performance. Energy and performance analysis on a 16-core mesh-based NoC topology running PARSEC and SPLASH-2 benchmark application traffic shows that our proposed router reduces the total energy by 17% and 23% respectively with negligible performance overhead.