The front-end chip of the SuperB SVT detector

被引：3

作者：

Giorgi, F. ^{[3
,4
]}

Comotti, D. ^{[1
]}

Manghisoni, M. ^{[1
,2
]}

Re, V. ^{[1
,2
]}

Traversi, G. ^{[1
,2
]}

Fabbri, L. ^{[3
,4
]}

Gabrielli, A. ^{[3
,4
]}

Pellegrini, G. ^{[4
]}

Sbarra, C. ^{[4
]}

Semprini-Cesari, N. ^{[3
,4
]}

Valentinetti, S. ^{[3
,4
]}

Villa, M. ^{[3
,4
]}

Zoccoli, A. ^{[3
,4
]}

Berra, A. ^{[5
,6
]}

Lietti, D. ^{[5
,6
]}

Prest, M. ^{[5
,6
]}

Bevan, A. ^{[7
]}

Wilson, F. ^{[8
]}

Beck, G. ^{[7
]}

Morris, J. ^{[7
]}

Ganaway, F. ^{[7
]}

Cenci, R. ^{[9
]}

Bombelli, L. ^{[11
,12
]}

Citterio, M. ^{[12
]}

Coelli, S. ^{[12
]}

Fiorini, C. ^{[11
,12
]}

Liberali, V. ^{[10
,12
]}

Monti, M. ^{[12
]}

Nasri, B. ^{[11
,12
]}

Neri, N. ^{[12
]}

Palombo, F. ^{[10
,12
]}

Stabile, A. ^{[10
,12
]}

Balestri, G. ^{[18
]}

Batignani, G. ^{[16
,18
]}

Bernardelli, A. ^{[18
]}

Bettarini, S. ^{[16
,18
]}

Bosi, F. ^{[18
]}

Casarosa, G. ^{[16
,18
]}

Ceccanti, M. ^{[18
]}

Forti, F. ^{[16
,18
]}

Giorgi, M. A. ^{[16
,18
]}

Lusiani, A. ^{[17
,18
]}

Mammini, P. ^{[18
]}

Morsani, F. ^{[18
]}

Oberhof, B. ^{[16
,18
]}

Paoloni, E. ^{[16
,18
]}

Perez, A. ^{[18
]}

Petragnani, G. ^{[18
]}

Profeti, A. ^{[18
]}

Rizzo, G. ^{[16
,18
]}

机构：

[1] Univ Bergamo, Bergamo, Italy

[2] Ist Nazl Fis Nucl, Sez Pavia, Pavia, Italy

[3] Univ Bologna, I-40126 Bologna, Italy

[4] Ist Nazl Fis Nucl, Sez Bologna, Bologna, Italy

[5] Univ Insubria, Como, Italy

[6] Ist Nazl Fis Nucl, Sez Milano Bicocca, Milan, Italy

[7] Univ London, Sch Phys & Astron Queen Mary, London E1 4NS, England

[8] STFC Rutherford Appleton Lab, Didcot OX11 0QX, Oxon, England

[9] Univ Maryland, College Pk, MD 20742 USA

[10] Univ Milan, I-20122 Milan, Italy

[11] Politecn Milan, Milan, Italy

[12] Ist Nazl Fis Nucl, Sez Milano, Milan, Italy

[13] Univ Modena & Reggio Emilia, Modena, Italy

[14] Ist Nazl Fis Nucl, Sez Padova, Padua, Italy

[15] Univ Pavia, I-27100 Pavia, Italy

[16] Univ Pisa, I-56100 Pisa, Italy

[17] Scuola Normale Super Pisa, Pisa, Italy

[18] Ist Nazl Fis Nucl, Sez Pisa, Pisa, Italy

[19] Univ Trento, Trento, Italy

[20] Univ Trieste, I-34127 Trieste, Italy

[21] Ist Nazl Fis Nucl, Sez Trieste, Trieste, Italy

[22] Univ Udine, I-33100 Udine, Italy

来源：

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT | 2013年 / 718卷

关键词：

HEP; Tracker; Front end; Strip; Fast readout; ASIC; VLSI;

D O I：

10.1016/j.nima.2012.11.036

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The asymmetric e(+) e(-) collider SuperB is designed to deliver a high luminosity, greater than 10(36) cm(-2) S-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%. (C) 2012 Elsevier B.V. All rights reserved.

引用

页码：180 / 183

页数：4

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