Advances in Parallel Discrete Event Simulation for Electronic System-Level Design

Parallel discrete event simulation (PDES) carries the promise to exploit the explicit parallelism in an Electronic System-Level (ESL) design model by utilizing the parallel computing resources on a multi-core simulation host. Synchronous PDES parallelizes the threads in the same simulation cycles. In contrast, advanced out-of-order PDES aggressively breaks the simulation cycle barrier and allows threads in different cycles to run in parallel for the small cost of increased compile time for static dependency analysis. Both PDES approaches fully retain the System-Level Description Languages (SLDL) simulation semantics and result in standard-compliant simulation with accurate timing. Moreover, both significantly reduce the simulator run time. Overall, PDES is highly desirable for ESL design due to the constantly rising complexity of embedded systems which requires accurate and fast simulation. PDES approaches improve simulator performance by executing suitable threads in parallel on a multi-core host.