Schedulability Analysis of Preemptive and Nonpreemptive EDF on Partial Runtime-Reconfigurable FPGAs

被引：11

作者：

Guan, Nan ^{[1
]}

Deng, Qingxu ^{[1
]}

Gu, Zonghua ^{[2
]}

Xu, Wenyao ^{[3
]}

Yu, Ge ^{[1
]}

机构：

[1] Northeastern Univ, Inst Comp Software, Shenyang 110004, Peoples R China

[2] Hong Kong Univ Sci & Technol, Dept Comp Sci & Engn, Hong Kong, Hong Kong, Peoples R China

[3] Zhejiang Univ, Coll Elect Engn, Hangzhou 310027, Peoples R China

来源：

ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 2008年 / 13卷 / 04期

基金：

中国国家自然科学基金; 国家高技术研究发展计划(863计划);

关键词：

D O I：

10.1145/1391962.1391964

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Field Programmable Gate Arrays (FPGAs) are very popular in today's embedded systems design, and Partial Runtime-Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this article, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bounds for several variants of global preemptive/nonpreemptive EDF scheduling, and compare the performance of different utilization bound tests.

引用

页数：43

共 4 条

[1] AN INTEGRATED TOOL FLOW TO REALIZE RUNTIME-RECONFIGURABLE APPLICATIONS ON A NEW CLASS OF PARTIAL MULTI-CONTEXT FPGAS
Rullmann, Markus
Merker, Renate
Hinkelmann, Heiko
Zipf, Peter
Glesner, Manfred
FPL: 2009 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, 2009, : 92 - +
[2] POSTER ABSTRACT: Preemptive Uniprocessor EDF Schedulability Analysis with Preemption Costs Considered
Deutschbein, Calvin
Baruah, Sanjoy
PROCEEDINGS OF 2016 IEEE REAL-TIME SYSTEMS SYMPOSIUM (RTSS), 2016, : 368 - 368
[3] LAG-based schedulability analysis for preemptive global EDF scheduling with dynamic cache allocation
Lin, Yuhan
Deng, Qingxu
Han, Meiling
Feng, Zhiwei
Wang, Shumo
Peng, Qize
JOURNAL OF SYSTEMS ARCHITECTURE, 2024, 147
[4] Analysis of applicability of partial runtime reconfiguration in fault emulator in Xilinx FPGAs
Kafka, Leos
2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS, 2008, : 178 - 181

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