A prototype of a VHDL-based fault injection tool: description and application

被引：40
|
作者：
Baraza, JC [1 ]
Gracia, J [1 ]
Gil, D [1 ]
Gil, PJ [1 ]
机构：
[1] Univ Politecn Valencia, Escuela Univ Informat, Dept Informat Sistemas & Comp, Grp Sistemas Tolerantes Fallos, Valencia 46022, Spain
来源：
JOURNAL OF SYSTEMS ARCHITECTURE | 2002年 / 47卷 / 10期
关键词：
fault-tolerant systems (FTSs); fault modelling; error syndrome; FTS validation; VHDL-based fault injection; fault injection tool;
D O I：
10.1016/S1383-7621(01)00036-4
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents the prototype of an automatic and model-independent fault injection tool, to be used on an IBM-PC (or compatible) platform. The tool has been built around a commercial VHDL simulator and it is thought to implement different fault injection techniques. With this tool, a wide range of transient and permanent faults can be injected into medium-complexity models. Another remarkable aspect of the tool is the fact that it can analyse the results obtained from injection campaigns, in order to study the Error Syndrome of the system model and/or validate its fault-tolerance mechanisms. Some results of various fault injection campaigns carried out to validate the Dependability of a fault-tolerant microcomputer system are shown. We have analysed the pathology of the propagated errors, measured their latencies, and calculated both error detection and recovery latencies and coverages. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
收藏
页码：847 / 867
页数：21
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