Multilevel inverter modulation method with DC-link disturbance compensation

Multilevel inverters have emerged as the state of the art power conversion systems for high power medium voltage applications. However, like most power converter families, these inverters are nonlinear systems with dead times, voltage drops across the power semiconductors, load and supply dependent DC-links, that all together can generate considerable low frequency voltage and current distortion affecting negatively the quality of important variables of the global process powered by the inverter. In high power applications this can be very critical due to the amount of energy involved in non desirable harmonics. This paper presents a solution to these problems by including the disturbances in the modulation strategy. Results are presented for a nine level cascaded asymmetric inverter, showing how the algorithm rejects DC-link voltage ripple and compensates voltage drops and dead times of the converter. The proposed method is also compared to Multiple Carrier Phase Disposition PWM to highlight the differences obtained when using the compensation.