共 16 条
- [1] <200 nm Wafer-to-Wafer Overlay Accuracy in Wafer Level Cu/SiO2 Hybrid Bonding for BSI CIS [J]. 2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC), 2015,
- [2] 50 nm Overlay Accuracy for Wafer-to-wafer Bonding by High-precision Alignment Technologies [J]. 2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, : 1664 - 1671
- [3] 0.5 μm Pitch Wafer-to-wafer Hybrid Bonding with SiCN Bonding Interface for Advanced Memory [J]. 2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, : 1110 - 1114
- [4] Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding [J]. 2020 IEEE 70TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2020), 2020, : 216 - 222
- [5] RECENT DEVELOPMENTS IN FINE PITCH WAFER-TO-WAFER HYBRID BONDING WITH COPPER INTERCONNECT [J]. 2019 INTERNATIONAL WAFER LEVEL PACKAGING CONFERENCE (IWLPC), 2019,
- [6] Novel failure analysis techniques for 1.8 μm pitch wafer-to-wafer bonding [J]. 2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 92 - 96
- [7] Low Temperature and Fine Pitch Nanocrystalline Cu/SiCN Wafer-to-Wafer Hybrid Bonding [J]. 2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC, 2023, : 1105 - 1109
- [8] Scalable, sub 2μm Pitch, Cu/SiCN to Cu/SiCN Hybrid Wafer-to-Wafer Bonding Technology [J]. 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2017,
- [9] Towards 5μm interconnection pitch with Die-to-Wafer direct hybrid bonding [J]. IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 470 - 475
- [10] A Highly Reliable 1.4μm pitch Via-Last TSV Module for Wafer-to-Wafer Hybrid Bonded 3D-SOC Systems [J]. 2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2019, : 1035 - 1040