Precise Timing Analysis for Direct-Mapped Caches

被引：0

作者：

Andalam, Sidharta ^{[1
]}

Sinha, Roopak ^{[1
]}

Roop, Partha ^{[1
]}

Girault, Alain ^{[1
]}

Reineke, Jan ^{[1
]}

机构：

[1] TUM CREATE, Singapore, Singapore

来源：

2013 50TH ACM / EDAC / IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2013年

关键词：

Instruction; Direct-Mapped; Cache Analysis;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Safety-critical systems require guarantees on their worst-case execution times. This requires modelling of speculative hardware features such as caches that are tailored to improve the average-case performance, while ignoring the worst case, which complicates the Worst Case Execution Time (WCET) analysis problem. Existing approaches that precisely compute WCET suffer from state-space explosion. In this paper, we present a novel cache analysis technique for direct-mapped instruction caches with the same precision as the most precise techniques, while improving analysis time by up to 240 times. This improvement is achieved by analysing individual control points separately, and carrying out optimisations that are not possible with existing techniques.

引用

页数：10

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