Validating real-time constraints in embedded systems

被引：0

作者：

Shyamasundar, RK ^{[1
]}

Aghav, JV ^{[1
]}

机构：

[1] Tata Inst Fundamental Res, Bombay 400005, Maharashtra, India

来源：

2001 PACIFIC RIM INTERNATIONAL SYMPOSIUM ON DEPENDABLE COMPUTING, PROCEEDINGS | 2001年

关键词：

embedded systems; Esterel; real-time systems; synchronous languages; validation & verification;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

There is a growing demand for software tools that can assist in designing, analyzing and validating embedded real-time system applications. ESTEREL a synchronous language, is widely used in the development of embedded systems and hardware/software codesign. In this paper, we describe a method that uses timed annotations for ESTEREL programs that makes it possible to predict the timing constraints required to be satisfied by the embedded system. Using the specified annotations and the programming environment of ESTEREL we describe a method and a tool for validating the concrete realization relative to time-annotated ESTEREL specifications. Also, the method derives time constraints to be satisfied by the concrete architectures for realizing the logical specification. We shall illustrate the technique with examples as well as the structure of the tool implemented.

引用

页码：347 / 355

页数：9

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