A VSC-HVDC Model with Reduced Computational Intensity

The paper presents a simplified voltage-source converter (VSC) model to reduce the computational intensity of simulating a power system with embedded converters. This simplified model is based on the concept of dynamic average-value modeling and provides the ability to generate either the full spectrum or the fundamental-frequency component of the VSC voltage. The model is validated against a detailed model of a voltage-source converter based high voltage direct current (VSC-HVDC) circuit and shows accurate matching during steady state and transient operation. Simulation and validation results are obtained using an electromagnetic transient simulation program (PSCAD/EMTDC). A significant reduction in terms of central processing unit (CPU) time consumption is also achieved with the proposed models.