Evaluating High-Level Design Strategies on FPGAs for High-Performance Computing

被引:0
|
作者
Podobas, Artur [1 ]
Zohouri, Hamid Reza [1 ]
Maruyama, Naoya [1 ,2 ]
Matsuoka, Satoshi [1 ]
机构
[1] Tokyo Inst Technol, Tokyo, Japan
[2] RIKEN, Adv Inst Computat Sci, Wako, Saitama, Japan
基金
奥地利科学基金会;
关键词
FPGA; HLS; Nios; LegUp; OpenCL; Rodinia;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Field-Programmable Gate Arrays (FPGAs) are gaining considerable momentum in mainstream high-performance systems in recent years due to their flexibility and low power consumption. Still, FPGAs remain largely unavailable to software programmers due to programming and debugging difficulties that are inherent to standard Hardware Description Languages. The performance that hardware-oblivious software engineers can expect from migrating legacy code to FPGAs remains shrouded in mystery. To gain insight on how to use FPGAs in high-performance computing, we created four different systems and evaluated them using benchmarks from the Rodinia benchmark suite. The systems we evaluated were diverse with respect to both programming model and generality, and range from a custom-built 30-core manycore system to FSM-based accelerators using LegUP and deep data-flow pipelines using Intel FPGA SDK for OpenCL. We found that the original version of LegUp does not achieve very good performance out of the box; still, with some non-trivial modification in the architecture, we improved its performance by up to 10 times. Despite this, we found Intel FPGA SDK for OpenCL to perform up to two orders of magnitude faster than LegUp. We also found our general-purpose manycore system to have comparable performance with LegUp.
引用
收藏
页数:4
相关论文
共 50 条
  • [1] Evaluating High-Level Design Strategies on FPGAs for High-Performance Computing
    Podobas, Artur
    Zohouri, Hamid Reza
    Maruyama, Naoya
    Matsuoka, Satoshi
    [J]. 2017 27TH INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), 2017,
  • [2] Directive-Based, High-Level Programming and Optimizations for High-Performance Computing with FPGAs
    Lambert, Jacob
    Lee, Seyong
    Kim, Jungwon
    Vetter, Jeffrey S.
    Malony, Allen D.
    [J]. INTERNATIONAL CONFERENCE ON SUPERCOMPUTING (ICS 2018), 2018, : 160 - 171
  • [3] A Framework for Evaluating High-Level Design Methodologies for High-Performance Reconfigurable Computers
    El-Araby, Esam
    Merchant, Saumil G.
    El-Ghazawi, Tarek
    [J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2011, 22 (01) : 33 - 45
  • [4] Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
    Curreri, John
    Koehler, Seth
    Holland, Brian
    George, Alan D.
    [J]. PROCEEDINGS OF THE SIXTEENTH IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 2008, : 23 - 30
  • [5] Extending High-Level Synthesis with High-Performance Computing Performance Visualization
    Huthmann, Jens
    Podobas, Artur
    Sommer, Lukas
    Koch, Andreas
    Sano, Kentaro
    [J]. 2020 IEEE INTERNATIONAL CONFERENCE ON CLUSTER COMPUTING (CLUSTER 2020), 2020, : 371 - 380
  • [6] Transformations of High-Level Synthesis Codes for High-Performance Computing
    de Fine Licht, Johannes
    Besta, Maciej
    Meierhans, Simon
    Hoefler, Torsten
    [J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2021, 32 (05) : 1014 - 1029
  • [7] Integrating FPGAs in High-Performance Computing: Introduction
    Chow, Paul
    Hutton, Mike
    [J]. FPGA 2007: FIFTEENTH ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS, 2007, : 131 - 131
  • [8] FPGAs as Components in Heterogeneous High-Performance Computing Systems: Raising the Abstraction Level
    Vanderbauwhede, Wim
    Nabi, Syed Waqar
    [J]. PARALLEL COMPUTING: ON THE ROAD TO EXASCALE, 2016, 27 : 505 - 514
  • [9] Evaluating and Optimizing OpenCL Kernels for High Performance Computing with FPGAs
    Zohouri, Hamid Reza
    Maruyama, Naoya
    Smith, Aaron
    Matsuda, Motohiko
    Matsuoka, Satoshi
    [J]. SC '16: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE FOR HIGH PERFORMANCE COMPUTING, NETWORKING, STORAGE AND ANALYSIS, 2016, : 409 - 420
  • [10] An Automated High-level Design Framework for Partially Reconfigurable FPGAs
    Kumar, Rohit
    Gordon-Ross, Ann
    [J]. 2015 IEEE 29TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, 2015, : 170 - 175