An Ultralow-Power Low-Noise CMOS Biopotential Amplifier for Neural Recording

This brief presents a design strategy for a neural recording amplifier array with ultralow-power low-noise operation that is suitable for large-scale integration. The topology combines a highly efficient but supply-sensitive single-ended first stage with a shared reference channel and a differential second stage to effect feedforward supply noise cancellation, combining the low power of single-ended amplifiers with improved supply rejection. For a two-channel amplifier, the measurements show a midband gain of 58.7 dB and a passband from 490 mHz to 10.5 kHz. The amplifier consumes 2.85 mu A per channel from a 1-V supply and exhibits an input-referred noise of 3.04 mu V-rms from 0.1 Hz to 100 kHz, corresponding to a noise efficiency factor of 1.93. The power supply rejection ratio is better than 50 dB in the passband. The amplifier is fabricated in a 90-nm CMOS process and occupies 0.137 mm(2) of chip area.